Ok, I decided to kindo of do that, and since I don't have my PC with me now (I was on a trip, and now I'm back but I had to RMA my PSU...) I decided to try it on a mac. When I got the SSDT's I compared them to the ones I uploaded, and found they are the same. Are the SSDT's generated by the OS completly? Or maybe I accidentaly uploaded the SSDT's for the mac insted of my ASRock x58 Extreme, upps!.
Anyways, what I did was the following (in linux): acpidump -a 0x5FEB9E10 -l 0x1BA -o cst.dat and acpidump -a 0x5feb8f10 -l 0x85 -o cst1.dat. That should dump CPU0CST and CPU1CST.
What I got was the following:
Code:
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20081204
*
* Disassembly of cst1.dat, Sun Mar 21 16:50:06 2010
*
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000001BA (442)
* Revision 0x01
* Checksum 0x1A
* OEM ID "APPLE "
* OEM Table ID "Cpu0Cst"
* OEM Revision 0x00003001 (12289)
* Compiler ID "INTL"
* Compiler Version 0x20050309 (537199369)
*/
DefinitionBlock ("cst1.aml", "SSDT", 1, "APPLE ", "Cpu0Cst", 0x00003001)
{
External (PWRS)
External (PDC0)
External (CFGD)
External (\_PR_.CPU0, DeviceObj)
Scope (\_PR.CPU0)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
If (And (PDC0, 0x0300))
{
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
,)
},
0x02,
0x01,
0x01F4
}
})
}
}
If (LAnd (And (CFGD, 0x80), LNot (PWRS)))
{
Return (Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000416, // Address
,)
},
0x03,
0x39,
0x64
}
})
}
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x01,
0x01F4
}
})
}
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
}
})
}
}
}
Code:
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20081204
*
* Disassembly of cst1.dat, Sun Mar 21 17:02:09 2010
*
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000085 (133)
* Revision 0x01
* Checksum 0xE0
* OEM ID "APPLE "
* OEM Table ID "Cpu1Cst"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20050309 (537199369)
*/
DefinitionBlock ("cst1.aml", "SSDT", 1, "APPLE ", "Cpu1Cst", 0x00003000)
{
External (PDC1)
External (CFGD)
External (\_PR_.CPU1, DeviceObj)
External (\_PR_.CPU0._CST, IntObj)
Scope (\_PR.CPU1)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC1, 0x10
))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
Return (\_PR.CPU0._CST)
}
}
}
From what I can see in this post it seems I can just paste the Method (_CST, 0, NotSerialized) into the DSDT. This is a Core 2 Duo I'm working with now, but my PC has a i7 920, so would I get CPU0CST, CPU1CST, CPU2CST, etc or would I also get two or maybe one. If I get more than one -like in this case- how should I insert them into the DSDT? For my current DSDT I'm using the following procesor section:
Code:
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x0060,
0x0000015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},
0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0A)
{
Package (0x06)
{
0x00000A65,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},
Package (0x06)
{
0x00000A64,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},
Package (0x06)
{
0x000009DF,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},
Package (0x06)
{
0x0000095A,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},
Package (0x06)
{
0x000008D5,
0x00014438,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},
Package (0x06)
{
0x00000850,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},
Package (0x06)
{
0x000007CB,
0x0000F618,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},
Package (0x06)
{
0x00000746,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},
Package (0x06)
{
0x000006C1,
0x0000B798,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},
Package (0x06)
{
0x0000063C,
0x0000A7F8,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Could "extract" the necessary info from those dumps to build a Name (_CST, Package similar to that one? it seems much cleaner to me, and it fits in with the other processor parts.
Obviously, I won't be using this CST info because it dosn't belong to my hackintosh, but it seems like I can use it to "practice".
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