Memory controller in DSDT
Does anyone know what part of a Mac DSDTs that operates the memory controller?
- Primary Author
- @kDawg Published 2009-08-28
- Collection
- OSx86 Core & 10.X
- Archival Footprint
- 6,606 historical reads · 2 curated field notes (from 5 dispatches) · 2009-08-28 – 2009-09-12
- Credited Voices (3)
- @kDawg (3)@Firmware@uman
Does anyone know what part of a Mac DSDTs that operates the memory controller?
Author Updates & Technical Revisions
Follow-up dispatches by @kDawg
@FirmwareThere is no description of the "memory controller" in the DSDT. However, the part of the chipset containing the memory controller (northbridge) usually does a lot more stuff, and that is mentioned. What are you looking for in particular?
Just trying to cross-reference things in the lspci with devices in the DSDT.
For instance this device:
00:00.0 Host bridge [0600]: Intel Corporation Eaglelake DRAM Controller [8086:2e20] (rev 03)
I can't reference this with any functionality as far as OS X in concerned. The OS just seems to ignore it.
@umanFor Intel northbridges, you typically subtract 2 from the device id of your graphics device (in your case 2e12) to get the device id of the chipset "bridge". See: http://en.wikipedia.org/wiki/Intel_GMA ↗ for details. On both the MacBook X3100 and some HackBooks X3100, there is a device in ioreg called MCHC ("acpi-path" =…
Thanks for the great info!
Synthesized Community Field Notes
2 technical responses curated from 5 original dispatches
There is no description of the "memory controller" in the DSDT. However, the part of the chipset containing the memory controller (northbridge) usually does a lot more stuff, and that is mentioned. What are you looking for in particular?
For Intel northbridges, you typically subtract 2 from the device id of your graphics device (in your case 2e12) to get the device id of the chipset "bridge". See: http://en.wikipedia.org/wiki/Intel_GMA ↗ for details.
On both the MacBook X3100 and some HackBooks X3100, there is a device in ioreg called MCHC ("acpi-path" = "IOACPIPlane:/_SB/PCI0/MCHC@0") that is registered against the chipset bridge.
A good source for decoding some of the DSDT mysteries WRT to northbridges is here: tracker.core boot.org/trac/coreboot/browser/trunk/coreboot-v2/src/northbridge/intel/i945/acpi?rev=4455
-u
@kDawg00:00.0 Host bridge [0600]: Intel Corporation Eaglelake DRAM Controller [8086:2e20] (rev 03) I can't reference this with any functionality as far as OS X in concerned. The OS just seems to ignore it.