Does anyone know what part of a Mac DSDTs that operates the memory controller?

There is no description of the "memory controller" in the DSDT. However, the part of the chipset containing the memory controller (northbridge) usually does a lot more stuff, and that is mentioned. What are you looking for in particular?

Just trying to cross-reference things in the lspci with devices in the DSDT.

For instance this device:
00:00.0 Host bridge [0600]: Intel Corporation Eaglelake DRAM Controller [8086:2e20] (rev 03)

I can't reference this with any functionality as far as OS X in concerned. The OS just seems to ignore it.

For Intel northbridges, you typically subtract 2 from the device id of your graphics device (in your case 2e12) to get the device id of the chipset "bridge". See: http://en.wikipedia.org/wiki/Intel_GMA for details.

On both the MacBook X3100 and some HackBooks X3100, there is a device in ioreg called MCHC ("acpi-path" = "IOACPIPlane:/_SB/PCI0/MCHC@0") that is registered against the chipset bridge.

A good source for decoding some of the DSDT mysteries WRT to northbridges is here: http://tracker.coreboot.org/trac/cor.../acpi?rev=4455

-u

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MacBook Pro - have allergy to nickel in the aluminum casing. So my kid gets an expensive toy!

Gateway MX 8738 - Retail, vanilla Snow Leopard 10.6.2 (thanks kizwan!) with Chameleon RC4, modified DSDT. Upgraded to Core 2 CPU (easy to do). Upgraded to 640GB drive. Everything but SD card working. Minor niggles. GMA950 with QE/CI and *no* artifacts.

iMac (luxo/lamp) G4 with Tiger.

Thanks for the great info!!!!