Code:
Scope (\_PR)
{
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {
Name (_PPC, 0x00)
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x03)
{
Package (0x06)// P-State 0
{
3104, // f in MHz
75000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x00000820, // value written to PERF_CTL; fid=8, vid=32
0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
},
Package (0x06)// P-State 1
{
2716, // f in MHz
65000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000071C, // value written to PERF_CTL; fid=7, vid=28
0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
},
Package (0x06)// P-State 2
{
2328, // f in MHz
60000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000061A, // value written to PERF_CTL; fid=6, vid=26
0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
},
})
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06) {
Name (_PPC, 0x00)
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x03)
{
Package (0x06)// P-State 0
{
3104, // f in MHz
75000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x00000820, // value written to PERF_CTL; fid=8, vid=32
0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
},
Package (0x06)// P-State 1
{
2716, // f in MHz
65000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000071C, // value written to PERF_CTL; fid=7, vid=28
0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
},
Package (0x06)// P-State 2
{
2328, // f in MHz
60000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000061A, // value written to PERF_CTL; fid=6, vid=26
0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
},
})
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06) {
Name (_PPC, 0x00)
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x03)
{
Package (0x06)// P-State 0
{
3104, // f in MHz
75000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x00000820, // value written to PERF_CTL; fid=8, vid=32
0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
},
Package (0x06)// P-State 1
{
2716, // f in MHz
65000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000071C, // value written to PERF_CTL; fid=7, vid=28
0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
},
Package (0x06)// P-State 2
{
2328, // f in MHz
60000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000061A, // value written to PERF_CTL; fid=6, vid=26
0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
},
})
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06) {
Name (_PPC, 0x00)
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW, // PERF_CTL
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW, // PERF_STATUS
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x03)
{
Package (0x06)// P-State 0
{
3104, // f in MHz
75000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x00000820, // value written to PERF_CTL; fid=8, vid=32
0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
},
Package (0x06)// P-State 1
{
2716, // f in MHz
65000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000071C, // value written to PERF_CTL; fid=7, vid=28
0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
},
Package (0x06)// P-State 2
{
2328, // f in MHz
60000, // P in mW
10, // Transition latency in us
10, // Bus Master latency in us
0x0000061A, // value written to PERF_CTL; fid=6, vid=26
0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
},
})
}
}