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-   -   Vanilla speedstep (http://infinitemac.com/showthread.php?t=3477)

jinnggoff 07-20-2009 04:55 PM
Vanilla speedstep
 
Hi there
I was found some interesting about dsdt for speedstep
here is a link http://www.ztex.de/misc/c2ctl.e.html
here dsdt example form the site
Code:
Scope (\_PR)
{
    Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06) {

        Name (_PPC, 0x00)

        Name (_PCT, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_CTL
                    0x10,              // Bit Width
                    0x00,              // Bit Offset
                    0x0000000000000199, // Address
                    ,)
            },

            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_STATUS
                    0x10,              // Bit Width
                    0x00,    // Bit Offset
                    0x0000000000000198, // Address
                    ,)
            }
        })

        Name (_PSS, Package (0x03)
        {
            Package (0x06)// P-State 0
            {
                3104, // f in MHz
                75000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x00000820, // value written to PERF_CTL; fid=8, vid=32
                0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
            },

            Package (0x06)// P-State 1
            {
                2716, // f in MHz
                65000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000071C, // value written to PERF_CTL; fid=7, vid=28
                0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
            },

            Package (0x06)// P-State 2
            {
                2328, // f in MHz
                60000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000061A, // value written to PERF_CTL; fid=6, vid=26
                0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
            },
        })
    }

    Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06) {

        Name (_PPC, 0x00)

        Name (_PCT, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_CTL
                    0x10,              // Bit Width
                    0x00,              // Bit Offset
                    0x0000000000000199, // Address
                    ,)
            },

            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_STATUS
                    0x10,              // Bit Width
                    0x00,    // Bit Offset
                    0x0000000000000198, // Address
                    ,)
            }
        })

        Name (_PSS, Package (0x03)
        {
            Package (0x06)// P-State 0
            {
                3104, // f in MHz
                75000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x00000820, // value written to PERF_CTL; fid=8, vid=32
                0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
            },

            Package (0x06)// P-State 1
            {
                2716, // f in MHz
                65000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000071C, // value written to PERF_CTL; fid=7, vid=28
                0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
            },

            Package (0x06)// P-State 2
            {
                2328, // f in MHz
                60000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000061A, // value written to PERF_CTL; fid=6, vid=26
                0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
            },
        })
    }


    Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06) {

        Name (_PPC, 0x00)

        Name (_PCT, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_CTL
                    0x10,              // Bit Width
                    0x00,              // Bit Offset
                    0x0000000000000199, // Address
                    ,)
            },

            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_STATUS
                    0x10,              // Bit Width
                    0x00,    // Bit Offset
                    0x0000000000000198, // Address
                    ,)
            }
        })

        Name (_PSS, Package (0x03)
        {
            Package (0x06)// P-State 0
            {
                3104, // f in MHz
                75000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x00000820, // value written to PERF_CTL; fid=8, vid=32
                0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
            },

            Package (0x06)// P-State 1
            {
                2716, // f in MHz
                65000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000071C, // value written to PERF_CTL; fid=7, vid=28
                0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
            },

            Package (0x06)// P-State 2
            {
                2328, // f in MHz
                60000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000061A, // value written to PERF_CTL; fid=6, vid=26
                0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
            },
        })
    }


    Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06) {

        Name (_PPC, 0x00)

        Name (_PCT, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_CTL
                    0x10,              // Bit Width
                    0x00,              // Bit Offset
                    0x0000000000000199, // Address
                    ,)
            },

            ResourceTemplate ()
            {
                Register (FFixedHW, // PERF_STATUS
                    0x10,              // Bit Width
                    0x00,    // Bit Offset
                    0x0000000000000198, // Address
                    ,)
            }
        })

        Name (_PSS, Package (0x03)
        {
            Package (0x06)// P-State 0
            {
                3104, // f in MHz
                75000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x00000820, // value written to PERF_CTL; fid=8, vid=32
                0x00000820// value of PERF_STATE after successful transition; fid=8, vid=32
            },

            Package (0x06)// P-State 1
            {
                2716, // f in MHz
                65000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000071C, // value written to PERF_CTL; fid=7, vid=28
                0x0000071C// value of PERF_STATE after successful transition; fid=7, vid=28
            },

            Package (0x06)// P-State 2
            {
                2328, // f in MHz
                60000, // P in mW
                10, // Transition latency in us
                10, // Bus Master latency in us
                0x0000061A, // value written to PERF_CTL; fid=6, vid=26
                0x0000061A// value of PERF_STATE after successful transition; fid=6, vid=26
            },
        })
    }

}
I tried to my dsdt, but speedstep did not work :(

kizwan 07-20-2009 05:57 PM
@jinnggoff
Try set to "MacBook5,1" in your SMBIOS kext. Also try it with your original & modified DSDT. I have Intel Core 2 Duo T5600 with speedstep working in Mac OS X with original DSDT (aside HDEF & GFX modification). Or you can set to any of this:-
Code:
                                                <key>PLimitDict</key>
                                                <dict>
                                                        <key>MacBook5,1</key>
                                                        <integer>0</integer>
                                                        <key>MacBook5,2</key>
                                                        <integer>0</integer>
                                                        <key>MacBookPro5,1</key>
                                                        <integer>0</integer>
                                                        <key>MacBookPro5,2</key>
                                                        <integer>0</integer>
                                                        <key>MacPro3,1</key>
                                                        <integer>0</integer>
                                                        <key>Macmini3,1</key>
                                                        <integer>0</integer>
                                                        <key>iMac9,1</key>
                                                        <integer>0</integer>
                                                </dict>
This list is taken from:-
/System/Library/Extensions/IOPlatformPluginFamily.kext/Contents/PlugIns/ACPI_SMC_PlatformPlugin.kext/Contents/Info.plist

kizwan

jinnggoff 07-21-2009 11:17 AM
Hi Kizwan, Thanks for your suggest :), I have processor intel core 2 duo e6750....
when I tried every model mac, speedstep did not worked

wwbsox 09-04-2009 12:54 PM
speedstep on hack
 
setting my model to mac pro 3,1 allows speedstep to work somewhat. the multiplier will will switch from 6 at idle to 8.5 under load( changes processor frequency), but the voltage remains constantly at the highest p-state. I am currently looking at adding c-state and p-state info from SSDT's to the processor "scope" section of dsdt. I want to add all 6 possible p-states for my processor (Q9550).

xopher 10-15-2009 12:40 AM
May I ask, where did you get the information about all your available p-states? I've tried extracting DSDT, it only gives me 2 states, and VoodooMonitor, based on SuperHai's VoodooPower.kext, only gives me 3 p-states.

My CPU is a Q8400, 2.66Ghz.

Thanks

wwbsox 10-15-2009 01:44 AM
1 Attachment(s)
From what I have read... You should have one p-state for each multiplier for your processor.

I used CPUi. It gave me the following info.

adriangb 04-25-2010 06:08 PM
Have you tried extracting the P-States from the original tables? Search on one of your SSDT's (in case you have >1) for CPU0CST and CPU0IST. Under each one you will see two hex values, write them down on a piece of paper. Then boot into linux (I'll use Ubuntu here), connect to internet and run:
apt-get install acpidump
apt-get install iasl
acpidump -a 0xFIRSTHEXVALUEUNDERCPU0CST -l 0xSECONDVALUE > cpu0cst
acpidump -a 0xFIRSTHEXVALUEUNDERCPU0IST -l 0xSECONDVALUE > cpu0ist
iasl -d cpu0cst
iasl -d cpu0ist

If you have more than CPU0CST & IST (ex: CPU1IST) write, repeat the process for all of these (you probably only need the CPU0 ones, but you might as well do em all).
Then save them somewhere and reboot into OS X. Now open those files in DSDTSE. CPU0IST contains you P-States and CPU0CST you C-States. ATENTION: DO NOT COPY PASTE YOUR P-STATES INTO YOU DSDT, YOU HAVE TO MODIFY THEM SOME. How to do this is in this thread: http://www.insanelymac.com/forum/ind...owtopic=181631. The C-States might be mixed into some if and code, you'll have to get the right ones (and in the right order) from there.
I hope I got it all, and got it all right.

osmarbcn 08-03-2010 09:59 AM
Hello ,I have one problem with my Native Speedstep, is impossible what work for me, I use Smbios iMac 11.1 of the Multibeast, DSDT.aml P55 UD6 F10 and this not work for me, please some look my zip and you have more information for this problem, i no use any disabler kext, and AppleIntelCPUPowerManagement.kext I Have KP, I not understand why this not work for me. Please look my zip, have my extra and kexts and others screenshots.


Thanks


http://cl.ly/03a6b1eff146a76a3965

adriangb 08-03-2010 08:36 PM
1 Attachment(s)
I've been out of hackintoshing for some time now, so I'm not up to date with evereything. What I did see is that you had the C & P states in your DSDT & detection turned on (apparently a new feature that showed up). From what I understood after a quick read, you should have either one or the other & DropSSDT=Yes. The other thing I didn't understand was all those extra tables in you com.apple...
I changed some kexts and did a little editing to the DSDT, I doubt it will fix anything but give it a try.
(boot & Extra attached)