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#1
03-11-2010, 12:03 PM
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CST data, where it should come from and how to get it into the DSDT correctly.
I have an ASRock x58 Extreme, and the only thing that I'm missing is getting sleep to work.
In my DSDT I have the info for speedsteping on the i7 920, and I'm pleased to say that it works 100%. Along with that goes the CST info, and altho AppleLPC gets loaded and I get the "Restart automatically after power failure" option. I used to get the _CST evaluation failed... error, but I don't any more. The thing is, the dammed PC won't go to sleep (or more precisely, seems to go to sleep but reboots instead of waking up). I copied most of the CPU part of the DSDT from other boards, and modified it until it worked on mine. At first I thought that sleep should work, both my board and that one had up to C6 and the DSDT had 6 Package 0x4 or whatnot. But reading around, it seems that the address at which the CST info is located is in the SSDT, and that in order to insert it correctly in the DSDT it needs to be dumped from that address and then modified for the DSDT or something like that. So my question is: are the C-States generic or even thou they are the same state, do they contain info specific to each board? If so, then I would have to do all that dumping stuff, which I tried (and failed) to completely understand, could someone explain it to me or guide me thru it? I'm traveling right now, so I don't have the PC at hand, but I do have a mac and my DSDT/SSDT files, so I think I should be able to at least prepare a DSDT.aml that should work. Thank you very much in advance, attached are the files I think are relevant. 
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#2
03-18-2010, 05:04 AM
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Decent simple guide here: http://forum.thinkpads.com/viewtopic.php?f=32&t=85344
I had planned to go through the process, but I'm goingto hold off now, since my rig runs cool with VoodooPowerMini. By contrast, my MacBook Pro with C-States, native AppleCPUManagement runs too hot. I've started running VoodooMini on that with smcFanControl. Next week, I'll probably try opening it up and using Artic Silver, since it's out of AppleCare anyway... -- MacBook Pro - have allergy to nickel in the aluminum casing. So my kid gets an expensive toy!  Gateway MX 8738 - Retail, vanilla Snow Leopard 10.6.2 (thanks kizwan!) with Chameleon RC4, modified DSDT. Upgraded to Core 2 CPU (easy to do). Upgraded to 640GB drive. Everything but SD card working. Minor niggles. GMA950 with QE/CI and *no* artifacts.  iMac (luxo/lamp) G4 with Tiger.
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#3
03-18-2010, 05:47 AM
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Code:
The SSDT used in that guide has the folowing code:
Scope (\_PR.CPU0)
{
Name (C1M4, Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01, 0x01, 0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001014, // Address
,)
},
0x02, 0x01, 0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000001016, // Address
,)
},
0x03, 0x39, 0x64
}
})
My plain old "SSDT" has Code:
{
External (\_PR_.P001, DeviceObj)
Scope (\)
{
Name (SSDT, Package (0x03)
{
"CPU0IST ",
0xCBE901F0,
0x00001C0C
})
Name (CSDT, Package (0x03)
{
"CPU0CST ",
0xCBE91E00,
0x00000659
})
Name (TSDT, Package (0x03)
{
"CPU0TST ",
0x80000000,
0x80000000
})
Name (CFGD, 0x00200472)
Name (NCPU, 0x00000008)
Name (NPCP, 0x00000001)
Name (PDC0, 0x80000000)
Name (TBL0, 0x00)
Name (CTB0, 0x00)
Name (TTB0, 0x00)
Name (PSTE, 0x00)
Name (TSTE, 0x00)
OperationRegion (PMRG, SystemIO, 0x0800, 0x50)
Field (PMRG, ByteAcc, NoLock, Preserve)
{
Offset (0x41),
DEV4, 1,
DEV5, 1,
DEV6, 1,
DEV7, 1,
STS4, 1,
STS5, 1,
STS6, 1,
STS7, 1
}
}
Scope (\_PR.P001)
{
Name (HI0, 0x00)
Name (HC0, 0x00)
Name (HT0, 0x00)
Method (_PDC, 1, NotSerialized)
{
CreateDWordField (Arg0, 0x00, REVS)
CreateDWordField (Arg0, 0x04, SIZE)
Store (SizeOf (Arg0), Local0)
Store (Subtract (Local0, 0x08), Local1)
CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
Name (STS0, Buffer (0x04)
{
0x00, 0x00, 0x00, 0x00
})
Concatenate (STS0, TEMP, Local2)
_OSC (Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
}, REVS, SIZE, Local2)
}
Method (_OSC, 4, NotSerialized)
{
CreateDWordField (Arg3, 0x00, STS0)
CreateDWordField (Arg3, 0x04, CAP0)
CreateDWordField (Arg0, 0x00, IID0)
CreateDWordField (Arg0, 0x04, IID1)
CreateDWordField (Arg0, 0x08, IID2)
CreateDWordField (Arg0, 0x0C, IID3)
Name (UID0, Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
})
CreateDWordField (UID0, 0x00, EID0)
CreateDWordField (UID0, 0x04, EID1)
CreateDWordField (UID0, 0x08, EID2)
CreateDWordField (UID0, 0x0C, EID3)
If (LNot (LAnd (LAnd (LEqual (IID0, EID0), LEqual (IID1, EID1)),
LAnd (LEqual (IID2, EID2), LEqual (IID3, EID3)))))
{
Store (0x06, Index (STS0, 0x00))
Return (Arg3)
}
If (LNotEqual (Arg1, 0x01))
{
Store (0x0A, Index (STS0, 0x00))
Return (Arg3)
}
Or (And (PDC0, 0x7FFFFFFF), CAP0, PDC0)
If (LAnd (LAnd (LEqual (And (PDC0, 0x09), 0x09), LEqual (
TBL0, Zero)), LEqual (And (CFGD, 0x02), 0x02)))
{
Or (TBL0, 0x01, TBL0)
OperationRegion (GV00, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02
)))
Load (GV00, HI0)
}
If (LAnd (LAnd (LEqual (And (PDC0, 0x18), 0x18), LEqual (
CTB0, Zero)), LEqual (And (CFGD, 0x20), 0x20)))
{
Or (CTB0, 0x01, CTB0)
OperationRegion (CT00, SystemMemory, DerefOf (Index (CSDT, 0x01)), DerefOf (Index (CSDT, 0x02
)))
Load (CT00, HC0)
}
If (LAnd (LAnd (LEqual (And (PDC0, 0x04), 0x04), LEqual (
TTB0, Zero)), LEqual (And (CFGD, 0x00400000), 0x00400000)))
{
Or (TTB0, 0x01, TTB0)
OperationRegion (TT00, SystemMemory, DerefOf (Index (TSDT, 0x01)), DerefOf (Index (TSDT, 0x02
)))
Load (TT00, HT0)
}
Return (Arg3)
}
}
}
Code:
{
External (\_PR_.CPU1, DeviceObj)
External (\_PR_.CPU0, DeviceObj)
Scope (\)
{
Name (SSDT, Package (0x0C)
{
"CPU0IST ",
0x5FEBAC90,
0x0000022A,
"CPU1IST ",
0x5FEBAF10,
0x00000087,
"CPU0CST ",
0x5FEB9E10,
0x000001BA,
"CPU1CST ",
0x5FEB8F10,
0x00000085
})
Name (CFGD, 0x011B49B1)
Name (\PDC0, 0x80000000)
Name (\PDC1, 0x80000000)
Name (\SDTL, 0x00)
}
Scope (\_PR.CPU0)
{
Name (HI0, 0x00)
Name (HC0, 0x00)
Method (_PDC, 1, NotSerialized)
{
CreateDWordField (Arg0, 0x00, REVS)
CreateDWordField (Arg0, 0x04, SIZE)
Store (SizeOf (Arg0), Local0)
Store (Subtract (Local0, 0x08), Local1)
CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
Name (STS0, Buffer (0x04)
{
0x00, 0x00, 0x00, 0x00
})
Concatenate (STS0, TEMP, Local2)
_OSC (Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
}, REVS, SIZE, Local2)
}
Method (_OSC, 4, NotSerialized)
{
CreateDWordField (Arg3, 0x00, STS0)
CreateDWordField (Arg3, 0x04, CAP0)
CreateDWordField (Arg0, 0x00, IID0)
CreateDWordField (Arg0, 0x04, IID1)
CreateDWordField (Arg0, 0x08, IID2)
CreateDWordField (Arg0, 0x0C, IID3)
Name (UID0, Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
})
CreateDWordField (UID0, 0x00, EID0)
CreateDWordField (UID0, 0x04, EID1)
CreateDWordField (UID0, 0x08, EID2)
CreateDWordField (UID0, 0x0C, EID3)
If (LNot (LAnd (LAnd (LEqual (IID0, EID0), LEqual (IID1, EID1)),
LAnd (LEqual (IID2, EID2), LEqual (IID3, EID3)))))
{
Store (0x06, Index (STS0, 0x00))
Return (Arg3)
}
If (LNotEqual (Arg1, 0x01))
{
Store (0x0A, Index (STS0, 0x00))
Return (Arg3)
}
Or (And (PDC0, 0x7FFFFFFF), CAP0, PDC0)
If (And (CFGD, 0x01))
{
If (LAnd (LAnd (And (CFGD, 0x01000000), LEqual (And (PDC0,
0x09), 0x09)), LNot (And (SDTL, 0x01))))
{
Or (SDTL, 0x01, SDTL)
OperationRegion (IST0, SystemMemory, DerefOf (Index (SSDT, 0x01)), DerefOf (Index (SSDT, 0x02
)))
Load (IST0, HI0)
}
}
If (And (CFGD, 0xF0))
{
If (LAnd (LAnd (And (CFGD, 0x01000000), And (PDC0, 0x18
)), LNot (And (SDTL, 0x02))))
{
Or (SDTL, 0x02, SDTL)
OperationRegion (CST0, SystemMemory, DerefOf (Index (SSDT, 0x07)), DerefOf (Index (SSDT, 0x08
)))
Load (CST0, HC0)
}
}
Return (Arg3)
}
}
Scope (\_PR.CPU1)
{
Name (HI1, 0x00)
Name (HC1, 0x00)
Method (_PDC, 1, NotSerialized)
{
CreateDWordField (Arg0, 0x00, REVS)
CreateDWordField (Arg0, 0x04, SIZE)
Store (SizeOf (Arg0), Local0)
Store (Subtract (Local0, 0x08), Local1)
CreateField (Arg0, 0x40, Multiply (Local1, 0x08), TEMP)
Name (STS1, Buffer (0x04)
{
0x00, 0x00, 0x00, 0x00
})
Concatenate (STS1, TEMP, Local2)
_OSC (Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
}, REVS, SIZE, Local2)
}
Method (_OSC, 4, NotSerialized)
{
CreateDWordField (Arg3, 0x00, STS1)
CreateDWordField (Arg3, 0x04, CAP1)
CreateDWordField (Arg0, 0x00, IID0)
CreateDWordField (Arg0, 0x04, IID1)
CreateDWordField (Arg0, 0x08, IID2)
CreateDWordField (Arg0, 0x0C, IID3)
Name (UID1, Buffer (0x10)
{
/* 0000 */ 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29, 0xBE, 0x47,
/* 0008 */ 0x9E, 0xBD, 0xD8, 0x70, 0x58, 0x71, 0x39, 0x53
})
CreateDWordField (UID1, 0x00, EID0)
CreateDWordField (UID1, 0x04, EID1)
CreateDWordField (UID1, 0x08, EID2)
CreateDWordField (UID1, 0x0C, EID3)
If (LNot (LAnd (LAnd (LEqual (IID0, EID0), LEqual (IID1, EID1)),
LAnd (LEqual (IID2, EID2), LEqual (IID3, EID3)))))
{
Store (0x06, Index (STS1, 0x00))
Return (Arg3)
}
If (LNotEqual (Arg1, 0x01))
{
Store (0x0A, Index (STS1, 0x00))
Return (Arg3)
}
Or (And (PDC1, 0x7FFFFFFF), CAP1, PDC1)
If (And (CFGD, 0x01))
{
If (LAnd (LAnd (And (CFGD, 0x01000000), LEqual (And (PDC1,
0x09), 0x09)), LNot (And (SDTL, 0x10))))
{
Or (SDTL, 0x10, SDTL)
OperationRegion (IST1, SystemMemory, DerefOf (Index (SSDT, 0x04)), DerefOf (Index (SSDT, 0x05
)))
Load (IST1, HI1)
}
}
If (And (CFGD, 0xF0))
{
If (LAnd (LAnd (And (CFGD, 0x01000000), And (PDC1, 0x18
)), LNot (And (SDTL, 0x20))))
{
Or (SDTL, 0x20, SDTL)
OperationRegion (CST1, SystemMemory, DerefOf (Index (SSDT, 0x0A)), DerefOf (Index (SSDT, 0x0B
)))
Load (CST1, HC1)
}
}
Return (Arg3)
}
}
}
If I'm just being blind and dumb, please do tell. Last edited by adriangb; 03-21-2010 at 06:20 PM. Reason: Changed [PHP] to [CODE]. I should have spotted that earlier
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#4
03-19-2010, 04:26 PM
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Sorry dude. I can't help you. I have not yet traveled down the CST road...
-- MacBook Pro - have allergy to nickel in the aluminum casing. So my kid gets an expensive toy! Gateway MX 8738 - Retail, vanilla Snow Leopard 10.6.2 (thanks kizwan!) with Chameleon RC4, modified DSDT. Upgraded to Core 2 CPU (easy to do). Upgraded to 640GB drive. Everything but SD card working. Minor niggles. GMA950 with QE/CI and *no* artifacts. iMac (luxo/lamp) G4 with Tiger.
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#6
03-21-2010, 02:16 PM
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Yeah, try posting responses to silencer on one of his threads. I posted the link before on http://forum.thinkpads.com/viewtopic.php?f=32&t=85344, but he's posted the same on insanely at: http://www.insanelymac.com/forum/ind...05&pid=1432200
He's pretty helpful, and I think he wants his guide to be a little more generic than just oriented to thinkpads. (And that's the real problem with all our posts-- they tend to be fairly specific to our hardware. That's why any attempts like prasys's, silencer's, etc that try to generically educate are great. My advice is that if you do figure things out, document it for yourself, and then take a look at what's published and see if you can do better (or at least help edit a noob-friendly guide) that explains and documents SSDT/C-States for generic hardware. Most of us stop (and I am just as guilty) when we get something working. But we need to pass on the knowledge. (I wish we had better community-editable Wikis-- the incessant posts, many full of outdated, inaccurate and just plain wrong information make finding what you need very difficult and time-consuming). Good luck. -- MacBook Pro - have allergy to nickel in the aluminum casing. So my kid gets an expensive toy! Gateway MX 8738 - Retail, vanilla Snow Leopard 10.6.2 (thanks kizwan!) with Chameleon RC4, modified DSDT. Upgraded to Core 2 CPU (easy to do). Upgraded to 640GB drive. Everything but SD card working. Minor niggles. GMA950 with QE/CI and *no* artifacts. iMac (luxo/lamp) G4 with Tiger.
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#7
03-21-2010, 06:16 PM
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Ok, I decided to kindo of do that, and since I don't have my PC with me now (I was on a trip, and now I'm back but I had to RMA my PSU...) I decided to try it on a mac. When I got the SSDT's I compared them to the ones I uploaded, and found they are the same. Are the SSDT's generated by the OS completly? Or maybe I accidentaly uploaded the SSDT's for the mac insted of my ASRock x58 Extreme, upps!.
Anyways, what I did was the following (in linux): acpidump -a 0x5FEB9E10 -l 0x1BA -o cst.dat and acpidump -a 0x5feb8f10 -l 0x85 -o cst1.dat. That should dump CPU0CST and CPU1CST. What I got was the following: Code:
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20081204
*
* Disassembly of cst1.dat, Sun Mar 21 16:50:06 2010
*
*
* Original Table Header:
* Signature "SSDT"
* Length 0x000001BA (442)
* Revision 0x01
* Checksum 0x1A
* OEM ID "APPLE "
* OEM Table ID "Cpu0Cst"
* OEM Revision 0x00003001 (12289)
* Compiler ID "INTL"
* Compiler Version 0x20050309 (537199369)
*/
DefinitionBlock ("cst1.aml", "SSDT", 1, "APPLE ", "Cpu0Cst", 0x00003001)
{
External (PWRS)
External (PDC0)
External (CFGD)
External (\_PR_.CPU0, DeviceObj)
Scope (\_PR.CPU0)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
If (And (PDC0, 0x0300))
{
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
,)
},
0x02,
0x01,
0x01F4
}
})
}
}
If (LAnd (And (CFGD, 0x80), LNot (PWRS)))
{
Return (Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x01,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000416, // Address
,)
},
0x03,
0x39,
0x64
}
})
}
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x01,
0x01F4
}
})
}
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
}
})
}
}
}
Code:
/*
* Intel ACPI Component Architecture
* AML Disassembler version 20081204
*
* Disassembly of cst1.dat, Sun Mar 21 17:02:09 2010
*
*
* Original Table Header:
* Signature "SSDT"
* Length 0x00000085 (133)
* Revision 0x01
* Checksum 0xE0
* OEM ID "APPLE "
* OEM Table ID "Cpu1Cst"
* OEM Revision 0x00003000 (12288)
* Compiler ID "INTL"
* Compiler Version 0x20050309 (537199369)
*/
DefinitionBlock ("cst1.aml", "SSDT", 1, "APPLE ", "Cpu1Cst", 0x00003000)
{
External (PDC1)
External (CFGD)
External (\_PR_.CPU1, DeviceObj)
External (\_PR_.CPU0._CST, IntObj)
Scope (\_PR.CPU1)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC1, 0x10
))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
Return (\_PR.CPU0._CST)
}
}
}
Code:
Processor (\_PR.CPU0, 0x00, 0x00000410, 0x06)
{
Name (_CST, Package (0x07)
{
0x06,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x0060,
0x0000015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x0001,
0x000003E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
,)
},
0x02,
0x0040,
0x000001F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000415, // Address
,)
},
0x03,
0x0060,
0x0000015E
}
})
Name (_PCT, Package (0x02)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000199, // Address
,)
},
ResourceTemplate ()
{
Register (FFixedHW,
0x10, // Bit Width
0x00, // Bit Offset
0x0000000000000198, // Address
,)
}
})
Name (_PSS, Package (0x0A)
{
Package (0x06)
{
0x00000A65,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000015,
0x00000015
},
Package (0x06)
{
0x00000A64,
0x0001FBD0,
0x0000000A,
0x0000000A,
0x00000014,
0x00000014
},
Package (0x06)
{
0x000009DF,
0x0001A9C8,
0x0000000A,
0x0000000A,
0x00000013,
0x00000013
},
Package (0x06)
{
0x0000095A,
0x000186A0,
0x0000000A,
0x0000000A,
0x00000012,
0x00000012
},
Package (0x06)
{
0x000008D5,
0x00014438,
0x0000000A,
0x0000000A,
0x00000011,
0x00000011
},
Package (0x06)
{
0x00000850,
0x000128E0,
0x0000000A,
0x0000000A,
0x00000010,
0x00000010
},
Package (0x06)
{
0x000007CB,
0x0000F618,
0x0000000A,
0x0000000A,
0x0000000F,
0x0000000F
},
Package (0x06)
{
0x00000746,
0x0000DEA8,
0x0000000A,
0x0000000A,
0x0000000E,
0x0000000E
},
Package (0x06)
{
0x000006C1,
0x0000B798,
0x0000000A,
0x0000000A,
0x0000000D,
0x0000000D
},
Package (0x06)
{
0x0000063C,
0x0000A7F8,
0x0000000A,
0x0000000A,
0x0000000C,
0x0000000C
}
})
Method (_PPC, 0, NotSerialized)
{
Return (Zero)
}
}
Processor (\_PR.CPU1, 0x01, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU2, 0x02, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU3, 0x03, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU4, 0x04, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU5, 0x05, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU6, 0x06, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Processor (\_PR.CPU7, 0x07, 0x00000410, 0x06)
{
Alias (\_PR.CPU0._CST, _CST)
Alias (\_PR.CPU0._PCT, _PCT)
Alias (\_PR.CPU0._PSS, _PSS)
Alias (\_PR.CPU0._PPC, _PPC)
}
Obviously, I won't be using this CST info because it dosn't belong to my hackintosh, but it seems like I can use it to "practice".
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#8
03-30-2010, 03:53 AM
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Hey, I got my C-State info:
Code:
DefinitionBlock ("cst.aml", "SSDT", 1, "PmRef", "P001Cst", 0x00003001)
{
External (CFGD)
External (PDC0)
External (NCPU)
External (\_PR_.P008, DeviceObj)
External (\_PR_.P007, DeviceObj)
External (\_PR_.P006, DeviceObj)
External (\_PR_.P005, DeviceObj)
External (\_PR_.P004, DeviceObj)
External (\_PR_.P003, DeviceObj)
External (\_PR_.P002, DeviceObj)
External (\_PR_.P001, DeviceObj)
Scope (\_PR.P001)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (LGreater (NCPU, 0x01), LNot (And (PDC0, 0x10))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
If (LAnd (And (CFGD, 0x00200000), And (PDC0, 0x0200)))
{
If (And (CFGD, 0x80))
{
Return (Package (0x05)
{
0x04,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x11,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x11,
0x015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000030, // Address
0x01, // Access Size
)
},
0x03,
0x11,
0xC8
}
})
}
If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40
)))
{
Return (Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x11,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000020, // Address
0x01, // Access Size
)
},
0x03,
0x11,
0x015E
}
})
}
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000010, // Address
0x01, // Access Size
)
},
0x02,
0x11,
0x01F4
}
})
}
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x01, // Bit Width
0x02, // Bit Offset
0x0000000000000000, // Address
0x01, // Access Size
)
},
0x01,
0x01,
0x03E8
}
})
}
If (And (CFGD, 0x00200000))
{
If (And (CFGD, 0x80))
{
Return (Package (0x05)
{
0x04,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x20,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000814, // Address
,)
},
0x02,
0x60,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000815, // Address
,)
},
0x03,
0x80,
0x015E
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000816, // Address
,)
},
0x03,
0xA0,
0xC8
}
})
}
If (LAnd (LNot (And (CFGD, 0x80)), And (CFGD, 0x40
)))
{
Return (Package (0x04)
{
0x03,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x20,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000814, // Address
,)
},
0x02,
0x60,
0x01F4
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000815, // Address
,)
},
0x03,
0x80,
0x015E
}
})
}
If (And (CFGD, 0x20))
{
Return (Package (0x03)
{
0x02,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x20,
0x03E8
},
Package (0x04)
{
ResourceTemplate ()
{
Register (SystemIO,
0x08, // Bit Width
0x00, // Bit Offset
0x0000000000000814, // Address
,)
},
0x02,
0x60,
0x01F4
}
})
}
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
}
})
}
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x01,
0x03E8
}
})
}
}
Scope (\_PR.P002)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
Return (\_PR.P001._CST ())
}
}
Scope (\_PR.P003)
{
Method (_CST, 0, NotSerialized)
{
If (LAnd (And (CFGD, 0x01000000), LNot (And (PDC0, 0x10
))))
{
Return (Package (0x02)
{
0x01,
Package (0x04)
{
ResourceTemplate ()
{
Register (FFixedHW,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
0x01,
0x9D,
0x03E8
}
})
}
Return (\_PR.P001._CST ())
}
}
Scope (\_PR.... UP TO CPU8!
}
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