10.7.4 AMD Kernel

[justinster123]

Originally Posted by The Connactic Well, Mountain Lion is here. For we AMD users, three options: change to Intel, stuck with Lion i386 64-bit suporting on FX line (or Snow Leo with full functionality for all other AMDs) or hope, crossing fingers, that someone wise enough to patch a working arch x64_86 kernel pops out of the blue. RAW, i tried the 64-bit kernel. Instant reboot, as you told me. But, remember, i have a plain Athlon II x2. No ssse. So the question is - assuming the problem affects Bulldozers as well - why does this happen? Any clue?

I tried the kernel on x86_64 on my amd Athlon X2 7550 and it booted to the point where launchd would start up. no further, just like booting without -legacy
it says verbosely "Kernel is LP64" meaning 64-bit i've tried all the possible boot combination but it's a no-go.
SSSE3 emulator, how can it be so hard? (theoretically speaking) because there's only 16 new instructions that SSSE3 introduced.. hmm...

[The Connactic]

But why it doesn't boot, Justin? That's the question!

Indeed, it doesn't boot even with ssse3-enabled AMD FX series, as RAW x86 said before, so it isn't just a sss3-related issue, tha could be solved with an emulator.

Now don't let me be misunderstood: the emulator is important, as it would grant a full working Lion for almost every AMD user. We're in Mountain Lion era, though; without a working patched x86_64 kernel, in addition to a sss3 emulator for non-Buldozer users, the AMD hackintoshes will slowly fall into obsolescence.

[felipeunix]

Do not think the fight is over. Mountain Lion is here!!

[The Connactic]

The fight isn't over, but for the fight to be won, it's not enought for Mountain Lion to be here if it does not roar in AMD Hackintoshes, lol.

[R:A:W:X86]

Originally Posted by justinster123 it says verbosely "Kernel is LP64" meaning 64-bit i've tried all the possible boot combination but it's a no-go.

Interesting.
The patched x86_64 Kernel works on my Intel machines as well.
I have some suspicions what could be the problem for the majority of us AMD users here...

Would be cool if some other people with old / "pre-Phenom" AMD CPUs could try.

Originally Posted by felipeunix Do not think the fight is over. Mountain Lion is here!!

The src has been released as well.

For some reason xnu-2050.7.9 does not build for me wo errors... (unpatched of course)

I am not sure what I am missing - Xcode 4.5 probably?!
The problem may also be, that I am still kinda little drunken due to yesterday.
Someone else has tried to compile the Kernel yet?

[akimoa]

i do have ML running just looking into the programms next too xcode we need wich prob be

cxxfilt-11

dtrace-96

kext_tools-268.7

but i cant figure out wich version of bootstrap_cmds it is

maybe someone else can ? meanwhile i dl new xcode .....i might get it up and running by tonite and give it a shot ..but my timeframe is limited so will se if i get it goin

[pipko]

Originally Posted by akimoa i do have ML running just looking into the programms next too xcode we need wich prob be cxxfilt-11 dtrace-96 kext_tools-268.7 but i cant figure out wich version of bootstrap_cmds it is maybe someone else can ? meanwhile i dl new xcode .....i might get it up and running by tonite and give it a shot ..but my timeframe is limited so will se if i get it goin

is your ML run on amd or intel?

[akimoa]

on a Commodore C16 +4

na on a MacBookPro

[The Connactic]

Originally Posted by R:A:W:X86 Interesting. The patched x86_64 Kernel works on my Intel machines as well. I have some suspicions what could be the problem for the majority of us AMD users here...

What would them be?

I tried to compile the kernel to no avail...

[sulphide]

Differences between AMD64 and EM64T
There are a small number of differences between each instruction set. Compilers generally produce binaries that target both AMD64 and EM64T, making the differences mainly of interest to compiler developers and operating system developers.


Currently
EM64T’s BSF and BSR instructions act differently when the source is 0 and the operand size is 32 bits. The processor sets the
zero flag and leaves the upper 32 bits of the destination undefined.

AMD64 supports 3DNow! instructions. This includes prefetch with the opcode 0x0F 0x0D and PREFETCHW, which are useful for hiding memory latency.

EM64T lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).

EM64T lacks some model-specific registers that are considered architectural to AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.

EM64T supports microcode update as in 32-bit mode, whereas AMD64 processors use a different microcode update format and control MSRs.

EM64T’s CPUID instruction is very vendor-specific, as is normal for x86-style processors.

EM64T supports the MONITOR and MWAIT instructions, used by operating systems to better deal with Hyper-threading.

AMD64 systems allow the use of the AGP aperture as an IO-MMU. Operating systems can take advantage of this to let normal PCI devices DMA to memory above 4 GiB. EM64T systems require the use of bounce buffers, which are slower.

SYSCALL and SYSRET are also only supported in IA-32e mode (not in compatibility mode) on EM64T. SYSENTER and SYSEXIT are supported in both modes.

Near branches with the 0×66 (operand size) prefix behave differently. One type of CPU clears only the top 32 bits,
while the other type clears the top 48 bits.

may smth. of this be the clue?